As programmable logic becomes more generic and versatile, the means for testing the product prior to shipment needs to become more versatile. Programmable array logic (PAL) devices are programmed by the customer. However, prior to shipment it is necessary to verify the AC/DC/functional performance of the device. Because a PAL is non-functional if not programmed, it is necessary to add special test futures to assure that the customer receives only products meeting certain specifications.
Previous test circuit methodologies provided only limited ability to test specific features of PAL devices. The test features were fixed and limited and if the need arose for more creative or comprehensive testing, the test could not be performed without a design change. In addition, previous test circuits would not always use the same circuitry as used by the customer.
Past efforts to add testability to PAL devices have included the use of extra input lines and extra product terms under specific input conditions. The extra input lines are sensed through the "AND" array and the extra product terms are multiplexed into the "OR" gate. These features have allowed for verification of programming circuitry for every input line and product term is well is determining the functionality of the SUM-OF-PRODUCTS term for every product term. These features have also been used to test the AC performance of the device.
There are several disadvantages to this method of testing. All input and feedback buffers are not fully testable. This type of test does not always provide a good correlation with actual device performance and does not test all possible outputs or output configurations. The paths used for the test are not the actual operational device paths that are to be guaranteed to the customer. Thus, the problem of correlating results to the internal circuit delays becomes an issue and can cause "slow" devices to be incorrectly approved. Furthermore, the asynchronous reset and synchronous preset functions are not fully tested, if they are tested at all.
Another method for testing the performance of an unprogrammed PAL device uses a special setup condition which will disable certain device features and force certain device conditions. This technique is used on the TICPAL16XX devices manufactured by Texas Instruments Inc. Under a special setup condition, the device enters a test mode. In the test mode, all false input buffers and the true and false feedback buffers are forced into a disabled state where it will appear logically as if the programmable cells the buffers address are all programmed. For outputs in a non-register configuration, one-half of the outputs will have the SUM-OF-PRODUCTS term forced to a logical "1" condition and the OUTPUT-ENABLE product term will be available for test. The other half will have the OUTPUT-ENABLE product term forced to a logical "1" condition and the SUM-OF-PRODUCTS term will be available for test. For outputs in the registered configuration, there is no OUTPUT-ENABLE product term; thus the SUM-OF-PRODUCTS term is always available for test in the test mode.
Disadvantages to this approach include:
1) Only true input buffers can be tested. PA0 2) Only certain tests can be performed on each non-registered output. One-half of the outputs can do only T.sub.plh and Tphl, the other half can do only T.sub.plz, and T.sub.pzl. Thus, T.sub.phz and T.sub.pzh cannot be done. PA0 3) Practice has shown this methodology to have little or no correlation to actual device performance which may be several nanoseconds slower than test results would imply.
Therefore, a need has arisen for PAL circuitry which can test the functions of a PAL device as if the device were in actual service.